File indexing completed on 2025-08-03 08:20:51
0001 #include "packet_hbd_fpga.h"
0002
0003
0004 #define HBD_MAX_MODULES 4
0005
0006 Packet_hbd_fpga::Packet_hbd_fpga(PACKET_ptr data)
0007 : Packet_w4 (data)
0008 {
0009 nr_modules = 0;
0010 if ( getHitFormat() == IDHBD_FPGA3SAMPLES)
0011 {
0012 HBD_NSAMPLES = 3;
0013 }
0014 else
0015 {
0016 HBD_NSAMPLES = 24;
0017 }
0018 std::cout << "Samples = " << HBD_NSAMPLES << std::endl;
0019 }
0020
0021 int *Packet_hbd_fpga::decode ( int *nwout)
0022 {
0023
0024 int *k;
0025
0026 int dlength = getDataLength();
0027
0028
0029 k = (int *) findPacketDataStart(packet);
0030 if (k == 0)
0031 {
0032 *nwout = 0;
0033 return 0;
0034 }
0035
0036
0037 int *iarr = new int[ 48 * HBD_NSAMPLES * HBD_MAX_MODULES ];
0038
0039
0040 decoded_data2 = new int[ HBD_MAX_MODULES ];
0041 decoded_data3 = new int[ HBD_MAX_MODULES ];
0042 decoded_data4 = new int[ HBD_MAX_MODULES ];
0043
0044 memset( iarr, 0, 48*HBD_NSAMPLES*4*HBD_MAX_MODULES);
0045 memset( decoded_data2, 0, 4*HBD_MAX_MODULES);
0046 memset( decoded_data3, 0, 4*HBD_MAX_MODULES);
0047 memset( decoded_data4, 0, 4*HBD_MAX_MODULES);
0048
0049 int pos = 0;
0050
0051 while ( pos < dlength - 10)
0052 {
0053 int i;
0054 for ( i = 0; i< 10; i++)
0055 {
0056 if ( (k[pos] & 0xF0000000) != 0x80000000 )
0057 {
0058 pos++;
0059 }
0060 else
0061 {
0062 break;
0063 }
0064 }
0065
0066 if ( (k[pos] & 0xF00FF000) == 0x800FF000 )
0067 {
0068 nr_modules++;
0069
0070
0071
0072 int log_mod_nr = k[pos] & 0xf;
0073 int l1_trig_nr = k[pos+1] & 0xfff;
0074 int beam_clock = k[pos+2] & 0xfff;
0075 int phys_mod_nr = k[pos+3] & 0x1f;
0076
0077
0078
0079
0080
0081
0082
0083 if ( log_mod_nr >= HBD_MAX_MODULES)
0084 {
0085 std::cout << __FILE__ << " " << __LINE__
0086 << " wrong logical module number " << log_mod_nr << std::endl;
0087 }
0088 else
0089 {
0090 decoded_data2[log_mod_nr] = l1_trig_nr;
0091 decoded_data3[log_mod_nr] = beam_clock;
0092 decoded_data4[log_mod_nr] = phys_mod_nr;
0093 }
0094 pos += 4;
0095 }
0096 else
0097 {
0098 delete [] iarr;
0099 delete [] decoded_data2;
0100 delete [] decoded_data3;
0101 delete [] decoded_data4;
0102 decoded_data2 = 0;
0103 decoded_data3 = 0;
0104 decoded_data4 = 0;
0105 *nwout = 0;
0106 return 0;
0107 }
0108
0109
0110 while ( (k[pos] & 0xF0002000) == 0x40002000 )
0111 {
0112 int adc = ( k[pos] & 0xfff);
0113 int f_channr = (( k[pos] >>16 ) & 0x3f);
0114 int f_modnr = (( k[pos] >>22 ) & 0x3);
0115 int slot = 48*HBD_NSAMPLES*f_modnr + HBD_NSAMPLES*f_channr ;
0116
0117
0118
0119 iarr[slot++] = adc;
0120 pos++;
0121 while ( (k[pos] & 0xF0002000) == 0x40000000 )
0122 {
0123 int channr = (( k[pos] >>16 ) & 0x3f);
0124 int modnr = (( k[pos] >>22 ) & 0x3);
0125 if ( channr != f_channr || f_modnr != modnr )
0126 {
0127
0128
0129 break;
0130 }
0131 adc = ( k[pos] & 0xfff);
0132
0133
0134
0135 iarr[slot++] = adc;
0136 pos++;
0137 }
0138
0139 }
0140 if ( (k[pos] & 0xF0000000) == 0x20000000 )
0141 {
0142
0143 pos++;
0144 }
0145 }
0146 *nwout = 48 * HBD_NSAMPLES * HBD_MAX_MODULES;
0147 return iarr;
0148
0149 }
0150
0151
0152 int Packet_hbd_fpga::iValue(const int ich, const int is)
0153 {
0154 if (ich < 0 || ich >= nr_modules *HBD_NSAMPLES*48) return 0;
0155 if (is < 0 || is >= HBD_NSAMPLES) return 0;
0156
0157 if (decoded_data1 == NULL )
0158 {
0159 if ( (decoded_data1 = decode(&data1_length))==NULL)
0160 return 0;
0161 }
0162
0163 return decoded_data1[ich*HBD_NSAMPLES + is];
0164 }
0165
0166
0167
0168
0169 int Packet_hbd_fpga::iValue(const int ich, const char *what)
0170 {
0171
0172
0173
0174
0175 if (strcmp(what,"TRIGGER") == 0)
0176 {
0177 if (decoded_data1 == NULL )
0178 {
0179 if ( (decoded_data1 = decode(&data1_length))==NULL)
0180 return 0;
0181 }
0182 if (ich < 0 || ich >= nr_modules) return 0;
0183
0184 return decoded_data2[ich];
0185 }
0186
0187 else if (strcmp(what,"BCLK") == 0)
0188 {
0189
0190 if (decoded_data1 == NULL )
0191 {
0192 if ( (decoded_data1 = decode(&data1_length))==NULL)
0193 return 0;
0194 }
0195 if (ich < 0 || ich >= HBD_MAX_MODULES) return 0;
0196
0197 return decoded_data3[ich];
0198 }
0199
0200
0201 else if (strcmp(what,"MODULEID") == 0)
0202 {
0203
0204 if (decoded_data1 == NULL )
0205 {
0206 if ( (decoded_data1 = decode(&data1_length))==NULL)
0207 return 0;
0208 }
0209 if (ich < 0 || ich >= HBD_MAX_MODULES) return 0;
0210
0211 return decoded_data4[ich];
0212 }
0213
0214 else if (strcmp(what,"NRMODULES") == 0)
0215 {
0216
0217 if (decoded_data1 == NULL )
0218 {
0219 if ( (decoded_data1 = decode(&data1_length))==NULL)
0220 return 0;
0221 }
0222
0223 return nr_modules;
0224 }
0225
0226 return 0;
0227 }
0228
0229
0230
0231
0232
0233
0234 void Packet_hbd_fpga::dump ( OSTREAM &os)
0235 {
0236 int i,j;
0237
0238 this->identify(os);
0239
0240 os << " Number of Modules: " << SETW(8) << iValue(0,"NRMODULES") << std::endl;
0241
0242 for (i = 0; i < iValue(0,"NRMODULES"); i++)
0243 {
0244 os << " Module # " << std::setw(2) << i
0245 << " Trigger: " << SETW(8) << iValue(i,"TRIGGER")
0246 << " Beam Clock: " << SETW(8) << iValue(i,"BCLK")
0247 << " Module Id: " << SETW(8) << iValue(i,"MODULEID")
0248 << std::endl;
0249 }
0250
0251 for (i = 0; i < iValue(0,"NRMODULES") * 48 ; i++)
0252 {
0253 os << std::setw(5) << i << " | " ;
0254 for ( j = 0; j < HBD_NSAMPLES; j++)
0255 {
0256 os << std::setw(5) << iValue(i,j);
0257 }
0258
0259 os << std::endl;
0260 }
0261 dumpErrorBlock(os);
0262 dumpDebugBlock(os);
0263
0264 }