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File indexing completed on 2025-08-03 08:20:38

0001 #ifndef __ONCS_SUBEVT_CONSTANTS_H
0002 #define __ONCS_SUBEVT_CONSTANTS_H
0003 
0004 /* the enum types for dump style */
0005 #define EVT_DECIMAL     1
0006 #define EVT_HEXADECIMAL 2
0007 #define EVT_OCTAL       3
0008 
0009 /* Misc. values  */
0010 #define MAX_OUTLENGTH 80000
0011 
0012 // the header length value
0013 #define SEVTHEADERLENGTH 4U
0014 
0015 
0016 
0017 // ---------------------------------------------------------------------
0018 //    IDCRAW requests the subevent to be copied without any decoding
0019 #define IDCRAW   0 
0020 
0021 // ---------------------------------------------------------------------
0022 //    IDDGEN uses the standard decoding method imbedded in the subevent
0023 //    header in the new data format
0024 #define IDDGEN    1 
0025 
0026 // ---------------------------------------------------------------------
0027 //    IDHCPY requests only the subevent header (or the Event header) to be
0028 //    copied:
0029 #define IDHCPY    2 
0030 
0031 // ---------------------------------------------------------------------
0032 //    the next methods < 10 use what we consider standard methods by
0033 //    now, i.e., no scheme proprietary to one particular hardware brand
0034 
0035 #define ID1STR    3 
0036 #define IDCSTR    4 
0037 #define ID2EVT    5 
0038 #define ID4EVT    6 
0039 #define ID2SUP    7 
0040 
0041 // ---------------------------------------------------------------------
0042 // the next methods are for the hammond/g-2 board.
0043 
0044 #define IDHAMMONDSET    31
0045 #define IDHAMMOND       32
0046 
0047 #define IDSAM           40
0048 
0049 #define IDMIZNHC        41
0050 
0051 #define IDDCFEM         51
0052 #define IDTECFEM        52
0053 
0054 #define IDSIS3300       55
0055 #define IDCAENV792      56
0056 #define IDCAENV785N     57
0057 
0058 #define IDFIFOBOARD     58
0059 #define IDRCPETDATA     59
0060 #define IDBSPETDATA     60
0061 #define IDUPPETDATA     61
0062 #define IDUPPETDATA_V104     62
0063 #define IDSIS3300R       65
0064 
0065 
0066 #define IDSRSV01          70
0067 #define IDUPPETPARAMS     71
0068 
0069 #define IDDRS4V1        81
0070 #define IDCAENV1742     85
0071 
0072 #define IDPCONTAINER     89
0073 
0074 #define IDFNALMWPC       90
0075 #define IDFNALMWPCV2     91
0076 #define IDDIGITIZERV1    92
0077 
0078 #define IDTPCFEEV1     97
0079 #define IDMVTXV0       98
0080 
0081 #define IDTPCFEEV2     99
0082 
0083 #define IDVMM3V1      102
0084 
0085 #define IDDREAMV0     103
0086 
0087 #define IDMVTXV1      104
0088 #define IDMVTXV2      105
0089 #define IDMVTXV3      106
0090 
0091 #define IDINTTV0      110
0092 
0093 #define IDTPCFEEV3     120
0094 #define IDTPCFEEV4     121
0095 #define IDTPCFEEV5     122
0096 #define IDTPCFEEV6     123
0097 
0098 #define IDGL1V0      140
0099 #define IDGL1V1      143
0100 #define IDGL1V2      144
0101 
0102 
0103 // the "level 0", meaning the raw untreated FEM data 
0104 
0105 #define IDBBC_DCM0    IDDCM0OFFSET + 1
0106 #define IDMVD_DCM0    IDDCM0OFFSET + 2
0107 #define IDDCH_DCM0    IDDCM0OFFSET + 3
0108 #define IDPC_DCM0     IDDCM0OFFSET + 4
0109 #define IDTEC_DCM0    IDDCM0OFFSET + 5
0110 #define IDRICH_DCM0   IDDCM0OFFSET + 6
0111 #define IDTOF_DCM0    IDDCM0OFFSET + 7
0112 #define IDPBSC_DCM0   IDDCM0OFFSET + 8
0113 #define IDPBGL_DCM0   IDDCM0OFFSET + 9
0114 #define IDMUTA_DCM0   IDDCM0OFFSET + 10
0115 #define IDMUTC_DCM0   IDDCM0OFFSET + 11
0116 #define IDMUID_DCM0   IDDCM0OFFSET + 12
0117 
0118 // the "level 1", FEM data zero-suppressed by the FPGA
0119 
0120 #define IDBBC_DCM1    IDDCM1OFFSET + 1
0121 #define IDMVD_DCM1    IDDCM1OFFSET + 2
0122 #define IDDCH_DCM1    IDDCM1OFFSET + 3
0123 #define IDPC_DCM1     IDDCM1OFFSET + 4
0124 #define IDTEC_DCM1    IDDCM1OFFSET + 5
0125 #define IDRICH_DCM1   IDDCM1OFFSET + 6
0126 #define IDTOF_DCM1    IDDCM1OFFSET + 7
0127 #define IDPBSC_DCM1   IDDCM1OFFSET + 8
0128 #define IDPBGL_DCM1   IDDCM1OFFSET + 9
0129 #define IDMUTA_DCM1   IDDCM1OFFSET + 10
0130 #define IDMUTC_DCM1   IDDCM1OFFSET + 11
0131 #define IDMUID_DCM1   IDDCM1OFFSET + 12
0132 
0133 // the "level 2", data further compressed by the DSP
0134 
0135 #define IDBBC_DCM2    IDDCM2OFFSET + 1
0136 #define IDMVD_DCM2    IDDCM2OFFSET + 2
0137 #define IDDCH_DCM2    IDDCM2OFFSET + 3
0138 #define IDPC_DCM2     IDDCM2OFFSET + 4
0139 #define IDTEC_DCM2    IDDCM2OFFSET + 5
0140 #define IDRICH_DCM2   IDDCM2OFFSET + 6
0141 #define IDTOF_DCM2    IDDCM2OFFSET + 7
0142 #define IDPBSC_DCM2   IDDCM2OFFSET + 8
0143 #define IDPBGL_DCM2   IDDCM2OFFSET + 9
0144 #define IDMUTA_DCM2   IDDCM2OFFSET + 10
0145 #define IDMUTC_DCM2   IDDCM2OFFSET + 11
0146 #define IDMUID_DCM2   IDDCM2OFFSET + 12
0147 
0148 
0149 
0150 #endif